ISA Mapper: A Compute and Hardware Agnostic Deep Learning Compiler
Matthew Sotoudeh, Anand Venkat, Michael Anderson, Evangelos Georganas,, Alexander Heinecke, Jason Knight

TL;DR
ISA Mapper is a versatile deep learning compiler that abstracts hardware specifics, enabling optimized code generation for diverse accelerators, improving performance significantly over existing solutions.
Contribution
It introduces a unified IR and a flexible scheduling framework that automates code generation across various hardware architectures for deep learning workloads.
Findings
Achieved 2-5x performance improvements on GEMMs and RNNs.
Successfully extracted matrix multiplication kernels from complex deep learning operations.
Demonstrated compatibility and performance gains on both new and existing hardware.
Abstract
Domain specific accelerators present new challenges and opportunities for code generation onto novel instruction sets, communication fabrics, and memory architectures. In this paper we introduce an intermediate representation (IR) which enables both deep learning computational kernels and hardware capabilities to be described in the same IR. We then formulate and apply instruction mapping to determine the possible ways a computation can be performed on a hardware system. Next, our scheduler chooses a specific mapping and determines the data movement and computation order. In order to manage the large search space of mappings and schedules, we developed a flexible framework that allows heuristics, cost models, and potentially machine learning to facilitate this search problem. With this system, we demonstrate the automated extraction of matrix multiplication kernels out of recent…
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Taxonomy
TopicsGraph Theory and Algorithms · Parallel Computing and Optimization Techniques · Advanced Graph Neural Networks
