Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM based FPGA

TL;DR

This paper introduces a low-complexity, dynamic priority-based error correction method for FPGA configuration memory, improving system reliability by considering task criticality and execution timing.

Contribution

It proposes a novel ECC scheme using SHA and parity-based codes, combined with a dynamic scheduling algorithm for targeted error correction based on task importance.

Findings

Reduces error correction overhead and time.

Enhances system reliability by prioritizing critical tasks.

Validates effectiveness through simulation results.

Abstract

Efficient low complexity error correcting code(ECC) is considered as an effective technique for mitigation of multi-bit upset (MBU) in the configuration memory(CM)of static random access memory (SRAM) based Field Programmable Gate Array (FPGA) devices. Traditional multi-bit ECCs have large overhead and complex decoding circuit to correct adjacent multibit error. In this work, we propose a simple multi-bit ECC which uses Secure Hash Algorithm for error detection and parity based two dimensional Erasure Product Code for error correction. Present error mitigation techniques perform error correction in the CM without considering the criticality or the execution period of the tasks allocated in different portion of CM. In most of the cases, error correction is not done in the right instant, which sometimes either suspends normal system operation or wastes hardware resources for less critical tasks. In this paper,we advocate for a dynamic priority-based hardware scheduling algorithm which chooses the tasks for error correction based on their area, execution period and criticality. The proposed method has been validated in terms of overhead due to redundant bits, error correction time and system reliability