Scalable NoC-based Neuromorphic Hardware Learning and Inference

TL;DR

This paper presents a scalable neuromorphic hardware architecture based on Network-on-Chip that supports in-hardware learning of spiking neural networks using STDP, enabling efficient, reconfigurable, and large-scale brain-inspired computation.

Contribution

It introduces a low-cost, scalable NoC-based SNN hardware with fully distributed in-hardware STDP learning, addressing limitations of previous implementations.

Findings

Successfully learned MNIST digits using the hardware

Explored trade-offs between speed, area, and energy

Provided a method to optimize architecture configuration

Abstract

Bio-inspired neuromorphic hardware is a research direction to approach brain's computational power and energy efficiency. Spiking neural networks (SNN) encode information as sparsely distributed spike trains and employ spike-timing-dependent plasticity (STDP) mechanism for learning. Existing hardware implementations of SNN are limited in scale or do not have in-hardware learning capability. In this work, we propose a low-cost scalable Network-on-Chip (NoC) based SNN hardware architecture with fully distributed in-hardware STDP learning capability. All hardware neurons work in parallel and communicate through the NoC. This enables chip-level interconnection, scalability and reconfigurability necessary for deploying different applications. The hardware is applied to learn MNIST digits as an evaluation of its learning capability. We explore the design space to study the trade-offs between speed, area and energy. How to use this procedure to find optimal architecture configuration is also discussed.