Influence of A-Posteriori Subcell Limiting on Fault Frequency in Higher-Order DG Schemes

TL;DR

This paper investigates how a-posteriori subcell limiting enhances fault resilience in high-order DG schemes, specifically in the ADER DG solver, by detecting and correcting hardware-induced soft errors.

Contribution

It demonstrates that a-posteriori limiting procedures inherently improve fault detection and correction, increasing the robustness of the DG solver against hardware errors.

Findings

Limiter detects and corrects hardware-induced faults.

Resilience is increased through element-local checkpointing.

Faults leading to fatal failures are effectively mitigated.

Abstract

Soft error rates are increasing as modern architectures require increasingly small features at low voltages. Due to the large number of components used in HPC architectures, these are particularly vulnerable to soft errors. Hence, when designing applications that run for long time periods on large machines, algorithmic resilience must be taken into account. In this paper we analyse the inherent resiliency of a-posteriori limiting procedures in the context of the explicit ADER DG hyperbolic PDE solver ExaHyPE. The a-posteriori limiter checks element-local high-order DG solutions for physical admissibility, and can thus be expected to also detect hardware-induced errors. Algorithmically, it can be interpreted as element-local checkpointing and restarting of the solver with a more robust finite volume scheme on a fine subgrid. We show that the limiter indeed increases the resilience of the DG algorithm, detecting and correcting particularly those faults which would otherwise lead to a fatal failure.