An Area Efficient 2D Fourier Transform Architecture for FPGA Implementation

TL;DR

This paper introduces an area-efficient 2D FFT architecture for FPGA that reuses butterfly units through a control scheme, significantly reducing hardware resources while maintaining performance.

Contribution

It proposes a novel FPGA-based 2D FFT design that reuses butterfly units to minimize area without increasing computation time.

Findings

Area reduced by a factor of log_N(2) compared to conventional designs

Simulation verified on Virtex-6 FPGA with negligible performance loss

Reuses butterfly units multiple times for resource efficiency

Abstract

Two-dimensional Fourier transform plays a significant role in a variety of image processing problems, such as medical image processing, digital holography, correlation pattern recognition, hybrid digital optical processing, optical computing etc. 2D spatial Fourier transformation involves large number of image samples and hence it requires huge hardware resources of field programmable gate arrays (FPGA). In this paper, we present an area efficient architecture of 2D FFT processor that reuses the butterfly units multiple times. This is achieved by using a control unit that sends back the previous computed data of N/2 butterfly units to itself for {log_2(N) - 1} times. A RAM controller is used to synchronize the flow of data samples between the functional blocks.The 2D FFT processor is simulated by VHDL and the results are verified on a Virtex-6 FPGA. The proposed method outperforms the conventional NxN point 2D FFT in terms of area which is reduced by a factor of log_N(2) with negligible increase in computation time.