A Shock-Optimized SECE Integrated Circuit

TL;DR

This paper introduces a fully integrated, low-power shock-optimized SECE circuit for piezoelectric energy harvesters, significantly increasing energy extraction efficiency from sporadic shocks.

Contribution

It presents a novel shock-optimized SECE interface with ultra-low quiescent current, high efficiency, and demonstrated superior energy harvesting performance in CMOS 40nm technology.

Findings

Achieves 91% electrical efficiency under shocks

Harvests 4.2 times more energy than standard circuits

Operates effectively with shocks as small as 8μJ every 100 seconds

Abstract

This paper presents a fully integrated, self-starting shock-optimized Synchronous Electric Charge Extraction (SECE) interface for piezoelectric harvesters (PEHs). After introducing a model of the electromechanical system under shocks, we prove that the SECE is the most appropriate electrical interface to maximize the harvested energy from our PEH. The proposed interface is then presented, both at system-and transistor-levels. Thanks to a dedicated sequencing, its quiescent current is as low as 30nA. This makes the proposed interface efficient even under time-spaced shocks occurring at sporadic and unpredictable rates. The circuit is for instance able to maintain its self-powered operation while harvesting very small shocks of 8uJ happening every 100 seconds. Our chip was fabricated in CMOS 40nm technology, and occupies a 0.55mm^2 core area. The measured maximum electrical efficiency under shocks reaches 91%. Under shocks, the harvested energy by the proposed shock-optimized SECE interface is 4.2 times higher than using a standard energy harvesting circuit, leading to the best shock FoM among prior art.