Studies on the energy and deep memory behaviour of a cache-oblivious, task-based hyperbolic PDE solver

TL;DR

This paper analyzes the energy consumption and memory behavior of a cache-oblivious, task-based PDE solver, highlighting how heterogeneous memory and task characteristics impact performance and energy efficiency.

Contribution

It demonstrates the effectiveness of cache-oblivious design in managing deep memory hierarchies and proposes hardware and runtime support for dynamic, heterogeneous task execution.

Findings

Deep memory access bursts impact energy efficiency.

Frequency reduction improves energy-to-solution but not burst effects.

Cache-oblivious implementation exploits deep, non-inclusive memory effectively.

Abstract

We study the performance behaviour of a seismic simulation using the ExaHyPE engine with a specific focus on memory characteristics and energy needs. ExaHyPE combines dynamically adaptive mesh refinement (AMR) with ADER-DG. It is parallelized using tasks, and it is cache efficient. AMR plus ADER-DG yields a task graph which is highly dynamic in nature and comprises both arithmetically expensive tasks and tasks which challenge the memory's latency. The expensive tasks and thus the whole code benefit from AVX vectorization, though we suffer from memory access bursts. A frequency reduction of the chip improves the code's energy-to-solution. Yet, it does not mitigate burst effects. The bursts' latency penalty becomes worse once we add Intel Optane technology, increase the core count significantly, or make individual, computationally heavy tasks fall out of close caches. Thread overbooking to hide away these latency penalties contra-productive with non-inclusive caches as it destroys the cache and vectorization character. In cases where memory-intense and computationally expensive tasks overlap, ExaHyPE's cache-oblivious implementation can exploit deep, non-inclusive, heterogeneous memory effectively, as main memory misses arise infrequently and slow down only few cores. We thus propose that upcoming supercomputing simulation codes with dynamic, inhomogeneous task graphs are actively supported by thread runtimes in intermixing tasks of different compute character, and we propose that future hardware actively allows codes to downclock the cores running particular task types.