A simple scheme of low phase noise microwave synthesizers based on the sub-sampling phase lock loop
Wenbing Li, Qiang Hao, Yuanbo Du, Shaoqing Huang, Peter Yun and, Zehuang Lu

TL;DR
This paper presents a simple, low-cost, low phase noise microwave synthesizer at 6.835 GHz using a sub-sampling phase lock loop, suitable for atomic clocks and physics experiments.
Contribution
The paper introduces a novel, simplified architecture for microwave synthesizers based on sub-sampling PLL, reducing complexity, power consumption, and cost.
Findings
Achieved phase noise of -121 dBc/Hz at 1 kHz offset
Demonstrated suitability for Rb atomic clocks with high stability
Simplified design reduces power and cost
Abstract
In this paper, we demonstrate a simple scheme of 6.835 GHz microwave frequency synthesizer based on the sub-sampling phase lock loop (PLL) technique. The application of the sub-sampling PLL is the key to simplify the architecture of the synthesizer in this scheme. A 100 MHz oven controlled crystal oscillator (OCXO) with ultra-low phase noise is used as the initial signal source. Then a dielectric resonant oscillator (DRO) of 6.8 GHz is directly phase locked to the 100 MHz OCXO utilizing the sub-sampling PLL. Benefiting from the sub-sampling PLL, the processes of microwave frequency multiplication and phase lock which are necessary in the development of microwave synthesizer are greatly simplified. Therefore, the architecture of the synthesizer is very simple. Correspondingly, the power consumption and cost of the synthesizer are low. The absolute phase noises of the 6.835 GHz output…
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Taxonomy
TopicsAdvanced Frequency and Time Standards · Atomic and Subatomic Physics Research · Cold Atom Physics and Bose-Einstein Condensates
