Sparse Winograd Convolutional neural networks on small-scale systolic arrays

TL;DR

This paper presents an FPGA-based accelerator combining sparse Winograd convolution, small-scale systolic arrays, and optimized memory layout, achieving high efficiency and speedup for deep learning tasks.

Contribution

It introduces a novel FPGA accelerator design that balances computation and memory support using sparse Winograd convolution and small systolic arrays.

Findings

Achieves 20x-30x energy efficiency improvements.

More than 5x speedup over dense implementations.

High computational resource utilization on FPGA.

Abstract

The reconfigurability, energy-efficiency, and massive parallelism on FPGAs make them one of the best choices for implementing efficient deep learning accelerators. However, state-of-art implementations seldom consider the balance between high throughput of computation power and the ability of the memory subsystem to support it. In this paper, we implement an accelerator on FPGA by combining the sparse Winograd convolution, clusters of small-scale systolic arrays, and a tailored memory layout design. We also provide an analytical model analysis for the general Winograd convolution algorithm as a design reference. Experimental results on VGG16 show that it achieves very high computational resource utilization, 20x ~ 30x energy efficiency, and more than 5x speedup compared with the dense implementation.