An Automated System for Checking Lithography Friendliness of Standard Cells

TL;DR

This paper introduces an automated system that detects and prevents lithography weakpoints caused by standard cells and their placement, improving manufacturability at advanced process nodes.

Contribution

It presents a novel software methodology for identifying problematic standard cells and their arrangements to mitigate lithography weakpoints during physical synthesis.

Findings

Standard cells can induce lithography weakpoints after placement and routing.

Abutted standard cell instances can cause lithography issues.

The system effectively reduces lithography weakpoints during design synthesis.

Abstract

At advanced process nodes, lithography weakpoints can exist in physical layouts of integrated circuit designs even if the layouts pass design rule checking (DRC). Existence of lithography weakpoints in a physical layout can cause manufacturability issues, which in turn can result in yield losses. In our experiments, we have found that specific standard cells have tendencies to create lithography weakpoints after their cell instances are placed and routed, even though each of these cells does not contain any lithography weakpoint before performing placement and routing. In addition, our experiments have shown that abutted standard cell instances can induce lithography weakpoints. Therefore, in this paper, we propose methodologies that are used in a novel software system for checking standard cells in terms of the aforementioned lithography issues. Specifically, the software system is capable of detecting and sorting problematic standard cells which are prone to generate lithography weakpoints, as well as reporting standard cells that should not be abutted. Methodologies proposed in this paper allow us to reduce or even prevent the generation of undesirable lithography weakpoints during the physical synthesis phase of designing a digital integrated circuit.