Performance Comparison of some Synchronous Adders

TL;DR

This paper compares various synchronous adder architectures in terms of speed, power, area, and energy efficiency using 32-bit addition in a 28nm CMOS technology, highlighting the most optimal designs for different metrics.

Contribution

It provides a comprehensive performance comparison of multiple adder architectures, including hybrid and partitioned designs, under a standard CMOS process.

Findings

Hybrid CCLA-RCA offers the best speed and energy efficiency.

Non-uniform input partitioned CSLA without BEC has the smallest area-delay product.

RCA with standard full adder is most efficient in power-delay-area product.

Abstract

This technical note compares the performance of some synchronous adders which correspond to the following architectures: i) ripple carry adder (RCA), ii) recursive carry lookahead adder (RCLA), iii) hybrid RCLA-RCA with the RCA used in the least significant adder bit positions, iv) block carry lookahead adder (BCLA), v) hybrid BCLA-RCA with the RCA used in the least significant adder bit positions, and vi) non-uniform input partitioned carry select adders (CSLAs) without and with the binary to excess-1 code (BEC) converter. The 32-bit addition was considered as an example operation. The adder architectures mentioned were implemented by targeting a typical case PVT specification (high threshold voltage, supply voltage of 1.05V and operating temperature of 25 degrees Celsius) of the Synopsys 32/28nm CMOS technology. The comparison leads to the following observations: i) the hybrid CCLA-RCA is preferable to the other adders in terms of the speed, the power-delay product, and the energy-delay product, ii) the non-uniform input partitioned CSLA without the BEC converter is preferable to the other adders in terms of the area-delay product, and iii) the RCA incorporating the full adder present in the standard digital cell library is preferable to the other adders in terms of the power-delay-area product.