Throughput Optimizations for FPGA-based Deep Neural Network Inference

TL;DR

This paper introduces FPGA-based architectures for deep neural network inference that significantly improve speed and energy efficiency by reusing weights and compressing matrices, outperforming traditional x86 systems.

Contribution

It presents novel FPGA architectures utilizing batch processing and pruning, achieving high throughput and energy efficiency for neural network inference.

Findings

Speed-up of inference by one order of magnitude

Surpasses x86 data throughput with lower energy consumption

Effective mitigation of data transfer bottlenecks

Abstract

Deep neural networks are an extremely successful and widely used technique for various pattern recognition and machine learning tasks. Due to power and resource constraints, these computationally intensive networks are difficult to implement in embedded systems. Yet, the number of applications that can benefit from the mentioned possibilities is rapidly rising. In this paper, we propose novel architectures for the inference of previously learned and arbitrary deep neural networks on FPGA-based SoCs that are able to overcome these limitations. Our key contributions include the reuse of previously transferred weight matrices across multiple input samples, which we refer to as batch processing, and the usage of compressed weight matrices, also known as pruning. An extensive evaluation of these optimizations is presented. Both techniques allow a significant mitigation of data transfers and speed-up the network inference by one order of magnitude. At the same time, we surpass the data throughput of fully-featured x86-based systems while only using a fraction of their energy consumption.