Improving Reliability, Security, and Efficiency of Reconfigurable Hardware Systems

TL;DR

This paper explores methods to enhance the efficiency, reliability, and security of FPGA-based reconfigurable hardware systems through partial dynamic reconfiguration, with applications in database, signal processing, satellite, and cryptography.

Contribution

It introduces novel techniques for on-the-fly data path optimization, fault countermeasures, and dynamic security transformations in FPGA systems.

Findings

Significant energy efficiency improvements achieved.

Enhanced fault tolerance for satellite FPGA systems.

Improved security against physical attacks in cryptographic FPGA implementations.

Abstract

In this treatise, my research on methods to improve efficiency, reliability, and security of reconfigurable hardware systems, i.e., FPGAs, through partial dynamic reconfiguration is outlined. The efficiency of reconfigurable systems can be improved by loading optimized data paths on-the-fly on an FPGA fabric. This technique was applied to the acceleration of SQL queries for large database applications as well as for image and signal processing applications. The focus was not only on performance improvements and resource efficiency, but also the energy efficiency has been significantly improved. In the area of reliability, countermeasures against radiation-induced faults and aging effects for long mission times were investigated and applied to SRAM-FPGA-based satellite systems. Finally, to increase the security of cryptographic FPGA-based implementations against physical attacks, i.e., side-channel and fault injection analysis as well as reverse engineering, it is proposed to transform static circuit structures into dynamic ones by applying dynamic partial reconfiguration.