New Thread Migration Strategies for NUMA Systems

TL;DR

This paper introduces new thread migration strategies for NUMA systems that leverage hardware counter data to enhance thread locality and affinity, significantly improving performance in parallel applications.

Contribution

The paper proposes novel thread migration strategies guided by hardware counter data to optimize performance in NUMA architectures, validated on NAS benchmarks.

Findings

Up to 70% performance improvement in low locality scenarios

Small performance degradation in high locality cases

Effective use of hardware counters for migration decisions

Abstract

Multicore systems present on-board memory hierarchies and communication networks that influence performance when executing shared memory parallel codes. Characterising this influence is complex, and understanding the effect of particular hardware configurations on different codes is of paramount importance. In previous works, monitoring information extracted from hardware counters at runtime has been used to characterise the behaviour of each thread in the parallel code in terms of the number of floating point operations per second, operational intensity, and latency of memory access. We propose to use this information to guide thread migration strategies that improve execution efficiency by increasing locality and affinity. Different configurations of NAS Parallel OpenMP benchmarks on multicores were used to validate the benefits of the proposed thread migration strategies. Our proposed strategies produce up to 70% improvement in scenarios where locality and affinity are low, there being a small degradation in performance for codes with high locality and affinity.