UVM Based Reusable Verification IP for Wishbone Compliant SPI Master Core

TL;DR

This paper demonstrates a reusable UVM-based verification IP for a Wishbone compliant SPI Master core, ensuring robust verification of embedded system communication protocols.

Contribution

It introduces a parameterized UVM verification environment for a Wishbone SPI Master core, enhancing reusability and robustness in verification processes.

Findings

Successful verification of the SPI Master core using UVM methodology

Coverage analysis confirms thorough testing of the design

Simulation results validate protocol and bus compliance

Abstract

The System on Chip design industry relies heavily on functional verification to ensure that the designs are bug-free. As design engineers are coming up with increasingly dense chips with much functionality, the functional verification field has advanced to provide modern verification techniques. In this paper, we present verification of a wishbone compliant Serial Peripheral Interface (SPI) Master core using a System Verilog based standard verification methodology, the Universal Verification Methodology (UVM). The reason for using UVM factory pattern with parameterized classes is to develop a robust and reusable verification IP. SPI is a full duplex communication protocol used to interface components most likely in embedded systems. We have verified an SPI Master IP core design that is wishbone compliant and compatible with SPI protocol and bus and furnished the results of our verification. We have used QuestaSim for simulation and analysis of waveforms, Integrated Metrics Center, Cadence for coverage analysis. We also propose interesting future directions for this work in developing reliable systems.