p-GaAs nanowire MESFETs with near-thermal limit gating

TL;DR

This paper presents a p-GaAs nanowire MESFET that uses Schottky barriers for gating, achieving near-thermal limit subthreshold swing and high performance without a gate insulator, advancing III-V CMOS technology.

Contribution

It introduces a gate-insulator-free p-GaAs nanowire MESFET with superior performance metrics, simplifying fabrication and enhancing device efficiency.

Findings

Subthreshold swing of 62 mV/dec, close to thermal limit

On-off ratio of approximately 10^5

High-frequency operation up to 10 kHz

Abstract

Difficulties in obtaining high-performance p-type transistors and gate insulator charge-trapping effects present two major challenges for III-V complementary metal-oxide semiconductor (CMOS) electronics. We report a p-GaAs nanowire metal-semiconductor field-effect transistor (MESFET) that eliminates the need for a gate insulator by exploiting the Schottky barrier at the metal-GaAs interface. Our device beats the best-performing p-GaSb nanowire metal-oxide-semiconductor field effect transistor (MOSFET), giving a typical sub-threshold swing of 62 mV/dec, within 4% of the thermal limit, on-off ratio $\sim 10^{5}$, on-resistance ~700 k$\Omega$, contact resistance ~30 k$\Omega$, peak transconductance 1.2 $\mu$S/$\mu$m and high-fidelity ac operation at frequencies up to 10 kHz. The device consists of a GaAs nanowire with an undoped core and heavily Be-doped shell. We carefully etch back the nanowire at the gate locations to obtain Schottky-barrier insulated gates whilst leaving the doped shell intact at the contacts to obtain low contact resistance. Our device opens a path to all-GaAs nanowire MESFET complementary circuits with simplified fabrication and improved performance.