Impact of Integrated Circuit Packaging on Synaptic Dynamics of Memristive Devices

TL;DR

This paper investigates how integrated circuit packaging affects the synaptic behavior of memristors, comparing their potentiation and depression with and without packaging parasitics using measured data and circuit models.

Contribution

It introduces a method to incorporate packaging parasitics into memristor models for more accurate simulation of synaptic dynamics.

Findings

Packaging parasitics influence memristor switching behavior.

Measured data and models show differences in potentiation and depression.

Simulation results highlight the importance of considering packaging effects.

Abstract

The memristor can be used as non volatile memory (NVM) and for emulating neuron behavior. It has the ability to switch between low resistance $R_{on}$ and high resistance values $R_{off}$, and exhibit the synaptic dynamic behaviour such as potentiation and depression. This paper presents a study on potentiation and depression of memristors in Quad Flat Pack. A comparison is drawn between the memristors with and without the impact of parasitics of packaging, using measured data and equivalent circuit models. The parameters in memristor and packaging models for the SPICE simulations were determined using measured data to reflect the memristor parasitics in Quad Flat Packs.