Characterization and Modeling of 28-nm FDSOI CMOS Technology down to Cryogenic Temperatures

TL;DR

This paper extensively characterizes and models 28-nm FDSOI CMOS technology at cryogenic temperatures, revealing key phenomena and providing models crucial for integrating these circuits with silicon qubits at deep cryogenic levels.

Contribution

It introduces a comprehensive cryogenic modeling approach for 28-nm FDSOI CMOS, including transfer characteristics and mobility trends down to 1.4 K, aiding future quantum-classical integration.

Findings

Mobility degradation observed in long pMOS at cryogenic temperatures.

Maximum hole mobility around 77 K for pMOS devices.

Development of physics-based cryogenic compact models for FDSOI CMOS.

Abstract

This paper presents an extensive characterization and modeling of a commercial 28-nm FDSOI CMOS process operating down to cryogenic temperatures. The important cryogenic phenomena influencing this technology are discussed. The low-temperature transfer characteristics including body-biasing are modeled over a wide temperature range (room temperature down to 4.2\,K) using the design-oriented simplified-EKV model. The trends of the free-carrier mobilities versus temperature in long and short-narrow devices are extracted from dc measurements down to 1.4\,K and 4.2\,K respectively, using a recently-proposed method based on the output conductance. A cryogenic-temperature-induced mobility degradation is observed on long pMOS, leading to a maximum hole mobility around 77\,K. This work sets the stage for preparing industrial design kits with physics-based cryogenic compact models, a prerequisite for the successful co-integration of FDSOI CMOS circuits with silicon qubits operating at deep-cryogenic temperatures.