Getting to the Bottom of Negative Capacitance FETs

TL;DR

This paper critically examines Negative Capacitance FETs, providing design guidelines and revealing limitations related to material choice, quantum effects, and non-linearity, while suggesting practical applications for voltage recovery.

Contribution

It introduces a new design rule based on capacitor networks and clarifies the limitations and potential uses of NC-FETs in existing MOSFET platforms.

Findings

State-of-the-art MOSFETs are unsuitable for small-SS NC-FETs without metal gates.

Quantum capacitance limits hysteresis-free small-SS achievement.

NC non-linearity can be engineered for a tradeoff between SS and hysteresis.

Abstract

In this paper, we take a fresh look at the physics and operation of Negative Capacitance FETs, and provide unambiguous feedback to the device designers by examining NC-FETs' design space for sub-60 mV/dec Subthreshold Swing (SS). Straightforward design rule is derived, for the first time, based on the capacitor network in NC-FETs. Contrary to many ongoing efforts, it is found that: 1) state-of-the-art MOSFET platforms, such as SOI, FinFET, 2D-FET etc., are not suitable for constructing small-SS NC-FETs, unless internal metal gate is introduced; 2) quantum capacitance prevents NC-FETs from achieving hysteresis-free small-SS, and low densityof-states (DOS) material can alleviate this issue, to some extent; 3) NC non-linearity can be engineered to reach a tradeoff between sub-60 SS and hysteresis; 4) it is more encouraging and practical to use NC to recycle subthreshold voltage loss in short-channel MOSFETs, and overdrive voltage (essentially a type of loss).