Design and Implementation of High-throughput PCIe with DMA Architecture between FPGA and PowerPC

TL;DR

This paper presents a high-throughput, resource-efficient PCIe DMA architecture between FPGA and PowerPC, achieving over 666 MB/s data transfer with compatibility and simple control mechanisms.

Contribution

The paper introduces a novel PCIe DMA architecture that maximizes throughput while minimizing FPGA resource usage, compatible with Xilinx FPGA and PowerPC systems.

Findings

Achieved data throughput of over 666 MB/s.

Designed a DMA engine with dual-location register storage.

Ensured compatibility with Xilinx PCIe core and VxWorks.

Abstract

We designed and implemented a direct memory access (DMA) architecture of PCI-Express(PCIe) between Xilinx Field Program Gate Array(FPGA) and Freescale PowerPC. The DMA architecture based on FPGA is compatible with the Xilinx PCIe core while the DMA architecture based on POWERPC is compatible with VxBus of VxWorks. The solutions provide a high-performance and low-occupancy alternative to commercial. In order to maximize the PCIe throughput while minimizing the FPGA resources utilization, the DMA engine adopts a novel strategy where the DMA register list is stored both inside the FPGA during initialization phase and inside the central memory of the host CPU. The FPGA design package is complemented with simple register access to control the DMA engine by a VxWorks driver. The design is compatible with Xilinx FPGA Kintex Ultrascale Family, and operates with the Xilinx PCIe endpoint Generation 1 with lane configurations x8. A data throughput of more than 666 MBytes/s(memory write with data from FPGA to PowerPC) has been achieved with the single PCIe Gen1 x8 lanes endpoint of this design, PowerPC and FPGA can send memory write request to each other.