A Microbenchmark Characterization of the Emu Chick
Jeffrey S. Young, Eric Hein, Srinivas Eswar, Patrick Lavin, Jiajia Li,, Jason Riedy, Richard Vuduc, Thomas M. Conte

TL;DR
The Emu Chick prototype system demonstrates efficient, predictable memory bandwidth utilization for certain workloads by migrating lightweight threads near memory, contrasting with traditional cache-based architectures.
Contribution
This paper extends single-node analysis of the Emu Chick to a multi-node setting, comparing its performance to simulation and traditional platforms, highlighting its efficiency and predictability.
Findings
Emu Chick achieves up to 65% of peak bandwidth on pointer chasing.
It uses memory bandwidth more efficiently than traditional architectures for basic operations.
Bandwidth utilization decreases for computationally intensive workloads like SpMV.
Abstract
The Emu Chick is a prototype system designed around the concept of migratory memory-side processing. Rather than transferring large amounts of data across power-hungry, high-latency interconnects, the Emu Chick moves lightweight thread contexts to near-memory cores before the beginning of each memory read. The current prototype hardware uses FPGAs to implement cache-less "Gossamer cores for doing computational work and a stationary core to run basic operating system functions and migrate threads between nodes. In this multi-node characterization of the Emu Chick, we extend an earlier single-node investigation (Hein, et al. AsHES 2018) of the the memory bandwidth characteristics of the system through benchmarks like STREAM, pointer chasing, and sparse matrix-vector multiplication. We compare the Emu Chick hardware to architectural simulation and an Intel Xeon-based platform. Our results…
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