AutoAccel: Automated Accelerator Generation and Optimization with Composable, Parallel and Pipeline Architecture
Jason Cong, Peng Wei, Cody Hao Yu, Peng Zhang

TL;DR
AutoAccel automates the generation and optimization of FPGA accelerators using a composable microarchitecture template and analytical modeling, significantly improving performance over software implementations.
Contribution
The paper introduces the CPP microarchitecture template and an analytical model, enabling automated and efficient FPGA accelerator generation from software programs.
Findings
AutoAccel accelerators outperform software by 72x on average.
The CPP microarchitecture reduces design space complexity.
Analytical model enables fast design exploration.
Abstract
CPU-FPGA heterogeneous architectures are attracting ever-increasing attention in an attempt to advance computational capabilities and energy efficiency in today's datacenters. These architectures provide programmers with the ability to reprogram the FPGAs for flexible acceleration of many workloads. Nonetheless, this advantage is often overshadowed by the poor programmability of FPGAs whose programming is conventionally a RTL design practice. Although recent advances in high-level synthesis (HLS) significantly improve the FPGA programmability, it still leaves programmers facing the challenge of identifying the optimal design configuration in a tremendous design space. This paper aims to address this challenge and pave the path from software programs towards high-quality FPGA accelerators. Specifically, we first propose the composable, parallel and pipeline (CPP) microarchitecture as a…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
