The Impact of On-chip Communication on Memory Technologies for Neuromorphic Systems

TL;DR

This paper discusses how emerging nanoscale non-volatile memory technologies can enhance on-chip communication networks in neuromorphic systems, addressing scalability and connectivity challenges for future intelligent computing architectures.

Contribution

It analyzes communication requirements in large-scale neuromorphic systems and explores how new memory technologies can improve on-chip routing and connectivity.

Findings

Existing neuromorphic routing approaches are evaluated.

New memory technologies can mitigate communication bottlenecks.

Differences between neuromorphic and conventional network-on-chip architectures are highlighted.

Abstract

Emergent nanoscale non-volatile memory technologies with high integration density offer a promising solution to overcome the scalability limitations of CMOS-based neural networks architectures, by efficiently exhibiting the key principle of neural computation. Despite the potential improvements in computational costs, designing high-performance on-chip communication networks that support flexible, large-fanout connectivity remains as daunting task. In this paper, we elaborate on the communication requirements of large-scale neuromorphic designs, and point out the differences with the conventional network-on-chip architectures. We present existing approaches for on-chip neuromorphic routing networks, and discuss how new memory and integration technologies may help to alleviate the communication issues in constructing next-generation intelligent computing machines.