Analysis of Dynamic Memory Bandwidth Regulation in Multi-core Real-Time Systems

TL;DR

This paper develops a theoretical framework for analyzing the worst-case response time of tasks in multi-core real-time systems under dynamic memory bandwidth regulation, addressing unpredictability caused by shared resource contention.

Contribution

It introduces a novel analysis method for worst-case response time considering dynamic memory bandwidth allocation, enabling better schedulability in memory-intensive real-time systems.

Findings

Response time computation reduces to a maximization problem.

Efficient solution for worst-case response time analysis.

Improved schedulability in avionics systems.

Abstract

One of the primary sources of unpredictability in modern multi-core embedded systems is contention over shared memory resources, such as caches, interconnects, and DRAM. Despite significant achievements in the design and analysis of multi-core systems, there is a need for a theoretical framework that can be used to reason on the worst-case behavior of real-time workload when both processors and memory resources are subject to scheduling decisions. In this paper, we focus our attention on dynamic allocation of main memory bandwidth. In particular, we study how to determine the worst-case response time of tasks spanning through a sequence of time intervals, each with a different bandwidth-to-core assignment. We show that the response time computation can be reduced to a maximization problem over assignment of memory requests to different time intervals, and we provide an efficient way to solve such problem. As a case study, we then demonstrate how our proposed analysis can be used to improve the schedulability of Integrated Modular Avionics systems in the presence of memory-intensive workload.