Electrically inert h-BN/bilayer graphene interface in all-2D-heterostructure FETs

TL;DR

This study demonstrates that an all-2D h-BN/bilayer graphene heterostructure significantly reduces potential fluctuations and trap responses at the interface, enabling high-performance BLG-FETs with minimal parasitic effects.

Contribution

It reveals the electrically inert nature of the h-BN/BLG heterointerface, leading to suppressed potential fluctuations and trap responses in all-2D heterostructure FETs.

Findings

Potential fluctuations reduced to ~1 meV

Off-current suppressed to measurement limit at 20 K

Trap/detrap responses undetectable in capacitance measurements

Abstract

Bilayer graphene field-effect transistors (BLG-FETs), unlike conventional semiconductors, are greatly sensitive to potential fluctuations due to the charged impurities in high-k gate stacks since the potential difference between two layers induced by the external perpendicular electrical filed is the physical origin behind the band gap opening. The assembly of BLG with layered h-BN insulators into van der Waals heterostructure has been widely recognized to achieve the superior electrical transport properties. However, the carrier response properties at the h-BN/BLG heterointerface, which control the device performance, have not yet been revealed due to the inevitably large parasitic capacitance. In this study, the significant reduction of potential fluctuations to ~1 meV is achieved in all-2-dimensional heterostructure BLG-FET on a quartz substrate, which results in the suppression of the off-current to the measurement limit at a small band gap of ~90 meV at 20 K. By capacitance measurement, we demonstrate that the electron trap/detrap response at such heterointerface is suppressed to undetectable level in the measurement frequency range. The electrically inert van der Waals heterointerface paves the way for the realization of future BLG electronics applications.