An FPGA Implementation of a Time Delay Reservoir Using Stochastic Logic

TL;DR

This paper introduces a stochastic logic FPGA implementation of a time delay reservoir, analyzing its performance and robustness, and proposing a re-seeding method to mitigate stochastic noise effects.

Contribution

It presents a novel FPGA-based stochastic logic reservoir design with a re-seeding technique to improve noise robustness and reduce area costs.

Findings

Performs well on noise-tolerant classification tasks

Re-seeding reduces stochastic noise impact

Significant area reduction with efficient binary-stochastic conversion

Abstract

This paper presents and demonstrates a stochastic logic time delay reservoir design in FPGA hardware. The reservoir network approach is analyzed using a number of metrics, such as kernel quality, generalization rank, performance on simple benchmarks, and is also compared to a deterministic design. A novel re-seeding method is introduced to reduce the adverse effects of stochastic noise, which may also be implemented in other stochastic logic reservoir computing designs, such as echo state networks. Benchmark results indicate that the proposed design performs well on noise-tolerant classification problems, but more work needs to be done to improve the stochastic logic time delay reservoirs robustness for regression problems. In addition, we show that the stochastic design can significantly reduce area cost if the conversion between binary and stochastic representations implemented efficiently.