Memristive LSTM network hardware architecture for time-series predictive modeling problem

TL;DR

This paper presents a hardware architecture for LSTM networks using memristors, aimed at improving time-series forecasting by leveraging neural network capabilities and hardware efficiency.

Contribution

It introduces a memristive hardware implementation of LSTM networks specifically designed for time-series prediction tasks.

Findings

Simulations performed with TSMC 0.18um CMOS technology.

Utilized HP memristor model for hardware simulation.

Demonstrated potential for efficient time-series forecasting hardware.

Abstract

Analysis of time-series data allows to identify long-term trends and make predictions that can help to improve our lives. With the rapid development of artificial neural networks, long short-term memory (LSTM) recurrent neural network (RNN) configuration is found to be capable in dealing with time-series forecasting problems where data points are time-dependent and possess seasonality trends. Gated structure of LSTM cell and flexibility in network topology (one-to-many, many-to-one, etc.) allows to model systems with multiple input variables and control several parameters such as the size of the look-back window to make a prediction and number of time steps to be predicted. These make LSTM attractive tool over conventional methods such as autoregression models, the simple average, moving average, naive approach, ARIMA, Holt's linear trend method, Holt's Winter seasonal method, and others. In this paper, we propose a hardware implementation of LSTM network architecture for time-series forecasting problem. All simulations were performed using TSMC 0.18um CMOS technology and HP memristor model.