Accelerating Viterbi Algorithm using Custom Instruction Approach

TL;DR

This paper proposes enhancing processor instruction sets with custom instructions to significantly accelerate the Viterbi decoding algorithm across different hardware architectures, improving execution time by up to three times.

Contribution

It introduces a custom instruction approach for Viterbi decoding, demonstrating substantial performance improvements on RISC, stack, and FPGA-based processors.

Findings

Execution time improved by approximately 3 times on DLX and PicoJava II.

Execution time improved by 2 times on NIOS II.

Custom instructions effectively accelerate complex decoding algorithms.

Abstract

In recent years, the decoding algorithms in communication networks are becoming increasingly complex aiming to achieve high reliability in correctly decoding received messages. These decoding algorithms involve computationally complex operations requiring high performance computing hardware, which are generally expensive. A cost-effective solution is to enhance the Instruction Set Architecture (ISA) of the processors by creating new custom instructions for the computational parts of the decoding algorithms. In this paper, we propose to utilize the custom instruction approach to efficiently implement the widely used Viterbi decoding algorithm by adding the assembly language instructions to the ISA of DLX, PicoJava II and NIOS II processors, which represent RISC, stack and FPGA-based soft-core processor architectures, respectively. By using the custom instruction approach, the execution time of the Viterbi algorithm is significantly improved by approximately 3 times for DLX and PicoJava II, and by 2 times for NIOS II.