Magic-State Functional Units: Mapping and Scheduling Multi-Level Distillation Circuits for Fault-Tolerant Quantum Architectures

TL;DR

This paper introduces optimized hardware units for quantum magic-state factories, employing novel mapping and scheduling techniques to significantly reduce space-time volume in fault-tolerant quantum architectures.

Contribution

It presents the first detailed designs of space-time optimized magic-state factories with new mapping and scheduling methods for surface code quantum computers.

Findings

Achieved a 5.64x reduction in space-time volume over previous designs.

Developed novel mapping techniques: braid repulsion and dipole moment braid rotation.

Enhanced routing efficiency through advanced scheduling and graph algorithms.

Abstract

Quantum computers have recently made great strides and are on a long-term path towards useful fault-tolerant computation. A dominant overhead in fault-tolerant quantum computation is the production of high-fidelity encoded qubits, called magic states, which enable reliable error-corrected computation. We present the first detailed designs of hardware functional units that implement space-time optimized magic-state factories for surface code error-corrected machines. Interactions among distant qubits require surface code braids (physical pathways on chip) which must be routed. Magic-state factories are circuits comprised of a complex set of braids that is more difficult to route than quantum circuits considered in previous work [1]. This paper explores the impact of scheduling techniques, such as gate reordering and qubit renaming, and we propose two novel mapping techniques: braid repulsion and dipole moment braid rotation. We combine these techniques with graph partitioning and community detection algorithms, and further introduce a stitching algorithm for mapping subgraphs onto a physical machine. Our results show a factor of 5.64 reduction in space-time volume compared to the best-known previous designs for magic-state factories.