Channel Characterization for Chip-scale Wireless Communications within Computing Packages

TL;DR

This paper models and analyzes wireless channels within chip packages to optimize antenna placement, revealing silicon content as a key factor affecting signal loss in chip-scale wireless communications.

Contribution

It provides a detailed modeling framework for flip-chip packages and investigates propagation characteristics, offering insights for optimizing wireless communication within and between chips.

Findings

Package configurations that minimize path loss identified

Silicon content significantly impacts signal attenuation

Single-chip and multi-chip architectures compared in terms of path loss

Abstract

Wireless Network-on-Chip (WNoC) appears as a promising alternative to conventional interconnect fabrics for chip-scale communications. WNoC takes advantage of an overlaid network composed by a set of millimeter-wave antennas to reduce latency and increase throughput in the communication between cores. Similarly, wireless inter-chip communication has been also proposed to improve the information transfer between processors, memory, and accelerators in multi-chip settings. However, the wireless channel remains largely unknown in both scenarios, especially in the presence of realistic chip packages. This work addresses the issue by accurately modeling flip-chip packages and investigating the propagation both its interior and its surroundings. Through parametric studies, package configurations that minimize path loss are obtained and the trade-offs observed when applying such optimizations are discussed. Single-chip and multi-chip architectures are compared in terms of the path loss exponent, confirming that the amount of bulk silicon found in the pathway between transmitter and receiver is the main determinant of losses.