Programmable Memristive Threshold Logic Gate Array
Olga Krestinskaya, Akshay Kumar Maan, Alex Pappachen James

TL;DR
This paper introduces a programmable threshold logic gate array using modified TLG cells, enabling high-speed processing with input-independent operation, implemented in 180nm CMOS technology, demonstrating efficient area and power metrics.
Contribution
It presents a novel TLG crossbar array architecture that operates independently of input signals and pulses, improving speed and efficiency.
Findings
On-chip area of 1463 μm² for 3x4 array
Power dissipation of 425 μW
Operation independent of input signals
Abstract
This paper proposes the implementation of programmable threshold logic gate (TLG) crossbar array based on modified TLG cells for high speed processing and computation. The proposed TLG array operation does not depend on input signal and time pulses, comparing to the existing architectures. The circuit is implemented using TSMC CMOS technology. The on-chip area and power dissipation of the simulated TLG array is and , respectively.
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
Taxonomy
TopicsAdvanced Memory and Neural Computing · Neuroscience and Neural Engineering · CCD and CMOS Imaging Sensors
