Scalable and Efficient Virtual Memory Sharing in Heterogeneous SoCs with TLB Prefetching and MMU-Aware DMA Engine

TL;DR

This paper introduces a scalable virtual memory sharing approach for heterogeneous SoCs that reduces TLB misses with prefetching, handles misses efficiently, and enables parallel DMA transfers without extra buffers, significantly improving performance.

Contribution

It presents a novel SVM solution with compiler-guided prefetching, parallel miss handling, and hardware support for DMA, enhancing scalability and efficiency in heterogeneous SoCs.

Findings

Up to 4x performance improvement for memory-intensive kernels.

60% performance gain for irregular memory access patterns.

Effective TLB miss reduction and parallel DMA support.

Abstract

Shared virtual memory (SVM) is key in heterogeneous systems on chip (SoCs), which combine a general-purpose host processor with a many-core accelerator, both for programmability and to avoid data duplication. However, SVM can bring a significant run time overhead when translation lookaside buffer (TLB) entries are missing. Moreover, allowing DMA burst transfers to write SVM traditionally requires buffers to absorb transfers that miss in the TLB. These buffers have to be overprovisioned for the maximum burst size, wasting precious on-chip memory, and stall all SVM accesses once they are full, hampering the scalability of parallel accelerators. In this work, we present our SVM solution that avoids the majority of TLB misses with prefetching, supports parallel burst DMA transfers without additional buffers, and can be scaled with the workload and number of parallel processors. Our solution is based on three novel concepts: To minimize the rate of TLB misses, the TLB is proactively filled by compiler-generated Prefetching Helper Threads, which use run-time information to issue timely prefetches. To reduce the latency of TLB misses, misses are handled by a variable number of parallel Miss Handling Helper Threads. To support parallel burst DMA transfers to SVM without additional buffers, we add lightweight hardware to a standard DMA engine to detect and react to TLB misses. Compared to the state of the art, our work improves accelerator performance for memory-intensive kernels by up to 4x and by up to 60% for irregular and regular memory access patterns, respectively.