Comparison of processing-induced deformations of InP bonded to Si determined by e-beam metrology: direct vs. adhesive bonding

TL;DR

This study uses electron beam metrology to compare deformation effects in InP-on-Si bonding methods, revealing how bonding and processing configurations influence alignment accuracy crucial for photonic device fabrication.

Contribution

It provides a detailed analysis of deformation sources in different bonding configurations, offering guidance to optimize fabrication processes for high-precision photonic devices.

Findings

Direct bonding with same-side patterning yields minimal deformation.

Bonding-induced deformations are significant in double-sided processing.

Mechanical wafer clamping affects multilayer alignment accuracy.

Abstract

In this paper, we employ an electron beam writer as metrology tool to investigate distortion of an exposed pattern of alignment marks in heterogeneously bonded InP on silicon. After experimental study of three different bonding and processing configurations which represent typical on-chip photonic device fabrication conditions, the smallest degree of linearly-corrected distortion errors is obtained for the directly bonded wafer, with the alignment marks both formed and measured on the same InP layer side after bonding (equivalent to single-sided processing of the bonded layer). Under these conditions, multilayer exposure alignment accuracy is limited by the InP layer deformation after the initial pattern exposure mainly due to the mechanical wafer clamping in the e-beam cassette. Bonding-induced InP layer deformations dominate in cases of direct and BCB bonding when the alignment marks are formed on one InP wafer side, and measured after bonding and substrate removal from another (equivalent to double-sided processing of the bonded layer). The findings of this paper provide valuable insight into the origin of the multilayer exposure misalignment errors for the bonded III-V on Si wafers, and identify important measures that need to be taken to optimize the fabrication procedures for demonstration of efficient and high-performance on-chip photonic integrated devices.