High-Accuracy and Fault Tolerant Stochastic Inner Product Design

TL;DR

This paper introduces a new stochastic inner product design that enhances accuracy, scalability, and fault tolerance in stochastic computing by using a two-line bipolar encoding and sequential processing.

Contribution

It proposes a novel inner product architecture that improves accuracy and scalability while reducing hardware costs in stochastic computing.

Findings

Outperforms existing designs in accuracy and fault tolerance.

Reduces hardware costs for high-precision applications.

Offers better scalability than traditional adder tree approaches.

Abstract

In this work, we present a novel inner product design for stochastic computing. Stochastic computing is an emerging computing technique, that encodes a number in the probability of observing a one in a random bit stream. This leads to reduced hardware costs and high error tolerance. The proposed inner product design is based on a two-line bipolar encoding format and applies sequential processing of the input in a central accumulation unit. Sequential processing significantly increases the computation accuracy, since it allows for preliminary cancelation of carry bits. Moreover, the central accumulation unit gives a much better scalability compared to conventional adder tree approaches. We show that the proposed inner product design outperforms state-of-the-art designs in terms of hardware costs for high accuracy requirements and fault tolerance.