Design-oriented Modeling of 28 nm FDSOI CMOS Technology down to 4.2 K for Quantum Computing

TL;DR

This paper extends the modeling of 28 nm FDSOI CMOS technology to cryogenic temperatures down to 4.2 K, incorporating effects like incomplete ionization and interface traps for quantum computing applications.

Contribution

It introduces a methodology to adapt industry-standard compact models for cryogenic temperatures, enabling accurate circuit design at 4.2 K.

Findings

EKV model accurately predicts temperature effects on device characteristics

Incomplete ionization significantly impacts device behavior at cryogenic temperatures

Models can be used for cryo-CMOS circuit design in quantum computing

Abstract

In this paper a commercial 28-nm FDSOI CMOS technology is characterized and modeled from room temperature down to 4.2 K. Here we explain the influence of incomplete ionization and interface traps on this technology starting from the fundamental device physics. We then illustrate how these phenomena can be accounted for in circuit device-models. We find that the design-oriented simplified EKV model can accurately predict the impact of the temperature reduction on the transfer characteristics, back-gate sensitivity, and transconductance efficiency. The presented results aim at extending industry-standard compact models to cryogenic temperatures for the design of cryo- CMOS circuits implemented in a 28 nm FDSOI technology.