D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput
Jeremie S. Kim, Minesh Patel, Hasan Hassan, Lois Orosa, Onur Mutlu

TL;DR
This paper introduces D-RaNGe, a novel DRAM-based true random number generator that exploits timing violations to produce high-quality, high-throughput randomness with low latency using commodity DRAM chips.
Contribution
It presents a new method to generate true random numbers by intentionally violating DRAM timing parameters, validated across multiple DRAM types and manufacturers.
Findings
Successfully passes NIST randomness tests
Achieves over two orders of magnitude higher throughput than previous DRAM TRNGs
Produces robust randomness across temperature and time variations
Abstract
We propose a new DRAM-based true random number generator (TRNG) that leverages DRAM cells as an entropy source. The key idea is to intentionally violate the DRAM access timing parameters and use the resulting errors as the source of randomness. Our technique specifically decreases the DRAM row activation latency (timing parameter tRCD) below manufacturer-recommended specifications, to induce read errors, or activation failures, that exhibit true random behavior. We then aggregate the resulting data from multiple cells to obtain a TRNG capable of providing a high throughput of random numbers at low latency. To demonstrate that our TRNG design is viable using commodity DRAM chips, we rigorously characterize the behavior of activation failures in 282 state-of-the-art LPDDR4 devices from three major DRAM manufacturers. We verify our observations using four additional DDR3 DRAM devices…
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Taxonomy
TopicsChaos-based Image/Signal Encryption · Physical Unclonable Functions (PUFs) and Hardware Security · Advanced Memory and Neural Computing
