The Effect of the Digit Slicing Architecture on the FFT Butterfly

TL;DR

This paper presents a digit slicing architecture for FFT butterfly implementation to enhance speed and efficiency in OFDM transceivers, validated through simulation and FPGA prototyping.

Contribution

It introduces a novel digit slicing based FFT butterfly design that balances speed and silicon area for FPGA implementation.

Findings

Achieved improved processing speed in FFT butterfly design.

Reduced silicon area compared to traditional architectures.

Validated design through MATLAB simulation and FPGA implementation.

Abstract

Most communications systems tend to achieve bandwidth, power and cost efficiencies to capable to describe modulation scheme. Hence for signal modulation, orthogonal frequency division multiplexing (OFDM) transceiver is introduced to cover communications demand in four generation. However high-performance Fast Fourier Transforms (FFT) as a main heart of OFDM acts beyond the view. In order to achieve capable FFT, design, and realization of its efficient internal structure is key issues of this research work. In this paper implementation of a high-performance butterfly for FFT by applying digit slicing technique is presented. The proposed design focused on the trade-off between the speed and active silicon area for the chip implementation. The new architecture was investigated and simulated with the MATLAB software. The Verilog HDL code in Xilinx ISE environment was derived to describe the FFT Butterfly functionality and was downloaded to Virtex II FPGA board.