An Overview of the Decimation process and Its VLSI Implementation

TL;DR

This paper reviews the decimation process in communication systems, focusing on sigma-delta modulators, and presents a hardware implementation with an improved arithmetic unit to enhance system efficiency.

Contribution

It provides a comprehensive overview of decimation and introduces an advanced arithmetic unit for better VLSI implementation of sigma-delta decimation.

Findings

Simulation results demonstrate improved system efficiency.

Hardware implementation confirms feasibility in Xilinx environment.

Enhanced arithmetic unit reduces processing complexity.

Abstract

Digital Decimation process plays an important task in a communication system. It mostly is applied in transceiver when the frequency reduction is required. However, the decimation process for sigma-delta modulator is considered in this research work. The proposed design was simulated using MATLAB software and implemented by hardware description language in Xilinx environment. Furthermore, the proposed advance arithmetic unit is applied to improve the system efficiency.