Memristor-based Synaptic Sampling Machines

TL;DR

This paper introduces a memristor-based hardware implementation of Synaptic Sampling Machines, leveraging memristive-CMOS crossbar structures to enable efficient, real-time neural network processing suitable for edge computing and IoT devices.

Contribution

It presents a novel circuit design for SSM neural networks using memristive-CMOS technology, facilitating hardware acceleration of synaptic sampling algorithms.

Findings

Demonstrates hardware feasibility of memristor-based SSM

Achieves potential for real-time processing in edge devices

Shows promising results in software simulations

Abstract

Synaptic Sampling Machine (SSM) is a type of neural network model that considers biological unreliability of the synapses. We propose the circuit design of the SSM neural network which is realized through the memristive-CMOS crossbar structure with the synaptic sampling cell (SSC) being used as a basic stochastic unit. The increase in the edge computing devices in the Internet of things era, drives the need for hardware acceleration for data processing and computing. The computational considerations of the processing speed and possibility for the real-time realization pushes the synaptic sampling algorithm that demonstrated promising results on software for hardware implementation.