Space Complexity of Implementing Large Shared Registers

TL;DR

This paper establishes fundamental space lower bounds for implementing large shared registers from smaller physical registers, considering various reader visibility scenarios and concurrency models.

Contribution

It introduces two new space lower bounds for shared register implementations, applicable to obstruction-free, lock-free, and wait-free settings, with tight bounds for certain cases.

Findings

At least eil((m-1)/(b-1)) physical registers are needed for invisible reader implementations.

A combined lower bound of eil(min((m-1)/(b-1), r + rac{\u221d m}{\u221d b})) applies generally.

Lower bounds hold even with atomic physical registers and regular implemented registers.

Abstract

We prove two new space lower bounds for the problem of implementing a large shared register using smaller physical shared registers. We focus on the case where both the implemented and physical registers are single-writer, which means they can be accessed concurrently by multiple readers but only by a single writer. To strengthen our lower bounds, we let the physical registers be atomic and we only require the implemented register to be regular. Furthermore, the lower bounds hold for obstruction-free implementations, which means they also hold for lock-free and wait-free implementations. If $m$ is the number values representable by the large register and $b$ is the number of values representable by each physical register, our first lower bound says that any obstruction-free implementation that has an invisible reader requires at least $\lceil \frac{m-1}{b-1} \rceil$ physical registers. A reader is considered invisible if it never writes to shared registers. This lower bound is tight for the invisible reader case. We also prove a $\lceil \min(\frac{m-1}{b-1}, r+\frac{\log{m}}{\log{b}}) \rceil$ space lower bound for the general case, which covers both visible and invisible readers. In this bound, $r$ represents the number of readers.