Network architecture for a topological quantum computer in silicon

TL;DR

This paper proposes a scalable silicon-based quantum computer architecture using a node/network design with electron shuttling, entanglement distribution, and surface code implementation, supported by simulations and error analysis.

Contribution

It introduces a novel large-scale surface code quantum processor design with minimal nodes and electron shuttling, enabling scalable quantum computing in silicon.

Findings

Electron shuttling is feasible without speed bottlenecks.

Error thresholds are estimated considering realistic noise models.

A protocol to convert non-Pauli noise into Pauli noise for efficient simulation.

Abstract

A design for a large-scale surface code quantum processor based on a node/network approach is introduced for semiconductor quantum dot spin qubits. The minimal node contains only 7 quantum dots, and nodes are separated on the micron scale, creating useful space for wiring interconnects and integration of conventional transistor circuits. Entanglement is distributed between neighbouring nodes by loading spin singlets locally and then shuttling one member of the pair through a linear array of empty dots. Each node contains one data qubit, two ancilla qubits, and additional dots to facilitate electron shuttling and measurement of the ancillas. A four-node GHZ state is realized by sharing three internode singlets followed by local gate operations and ancilla measurements. Further local operations and measurements produce an X or Z stabilizer on four data qubits, which is the fundamental operation of the surface code. Electron shuttling is simulated using a simplified gate electrode geometry without explicit barrier gates, and demonstrates that adiabatic transport is possible on timescales that do not present a speed bottleneck to the processor. An important shuttling error in a clean system is uncontrolled phase rotation due to the modulation of the electronic g-factor during transport, owing to the Stark effect. This error can be reduced by appropriate electrostatic tuning of the stationary electron's g-factor. Using reasonable noise models, we estimate error thresholds with respect to single and two-qubit gate fidelities as well as singlet dephasing errors during shuttling. A twirling protocol transforms the non-Pauli noise associated with exchange gate operations into Pauli noise, making it possible to use the Gottesman-Knill theorem to efficiently simulate large codes.