Circuits via topoi

TL;DR

This paper introduces a novel topos-theoretic semantics for sequential circuits, unifying time-sensitive and combinational gates within a single mathematical framework, and demonstrating their adherence to traced category theory.

Contribution

It applies topos theory to model sequential circuits, providing a unified semantics for different gate types and proving their compliance with traced category axioms.

Findings

Sequential circuits are modeled within the topos of presheaves over natural numbers.

Time-sensitive gates are treated uniformly with combinational gates in this framework.

The approach validates the equational theory of traced categories for these circuits.

Abstract

Leveraging topos theory a semantics can be given to sequential circuits where time-sensitive gates, such as unit delay, are treated uniformly with combinational gates. Both kinds of gates are functions in a particular topos: the topos of presheaves over the natural ordering of $\mathbb{N}$. This is used to show that sequential circuits validate the equational theory of traced categories.