Cross-layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach

TL;DR

This paper presents a machine learning-based framework for optimizing high-speed adder designs by predicting Pareto frontiers, effectively exploring a wide design space and bridging the gap between architectural and physical design stages.

Contribution

It introduces a novel active learning approach combined with an enhanced prefix adder synthesis algorithm to efficiently predict Pareto frontiers in physical design space.

Findings

Achieves high-quality Pareto frontiers across diverse adder architectures.

Reduces the need for extensive EDA tool runs through active learning.

Bridges the gap between architectural and physical design optimization.

Abstract

In spite of maturity to the modern electronic design automation (EDA) tools, optimized designs at architectural stage may become sub-optimal after going through physical design flow. Adder design has been such a long studied fundamental problem in VLSI industry yet designers cannot achieve optimal solutions by running EDA tools on the set of available prefix adder architectures. In this paper, we enhance a state-of-the-art prefix adder synthesis algorithm to obtain a much wider solution space in architectural domain. On top of that, a machine learning-based design space exploration methodology is applied to predict the Pareto frontier of the adders in physical domain, which is infeasible by exhaustively running EDA tools for innumerable architectural solutions. Considering the high cost of obtaining the true values for learning, an active learning algorithm is utilized to select the representative data during learning process, which uses less labeled data while achieving better quality of Pareto frontier. Experimental results demonstrate that our framework can achieve Pareto frontier of high quality over a wide design space, bridging the gap between architectural and physical designs.