Bridging the Gap Between Layout Pattern Sampling and Hotspot Detection via Batch Active Learning

TL;DR

This paper introduces an active learning approach to improve hotspot detection in VLSI layout design, reducing simulation costs while maintaining high detection accuracy across different lithography technologies.

Contribution

It proposes a novel active learning-based sampling method that optimizes both the training set and the detection model, enhancing efficiency and accuracy.

Findings

Reduces lithography simulation overhead significantly.

Achieves comparable or better detection accuracy with fewer training samples.

Effective across DUV and EUV lithography technologies.

Abstract

Layout hotpot detection is one of the main steps in modern VLSI design. A typical hotspot detection flow is extremely time consuming due to the computationally expensive mask optimization and lithographic simulation. Recent researches try to facilitate the procedure with a reduced flow including feature extraction, training set generation and hotspot detection, where feature extraction methods and hotspot detection engines are deeply studied. However, the performance of hotspot detectors relies highly on the quality of reference layout libraries which are costly to obtain and usually predetermined or randomly sampled in previous works. In this paper, we propose an active learning-based layout pattern sampling and hotspot detection flow, which simultaneously optimizes the machine learning model and the training set that aims to achieve similar or better hotspot detection performance with much smaller number of training instances. Experimental results show that our proposed method can significantly reduce lithography simulation overhead while attaining satisfactory detection accuracy on designs under both DUV and EUV lithography technologies.