Efficient DSP and Circuit Architectures for Massive MIMO: State-of-the-Art and Future Directions

TL;DR

This paper reviews recent advances in energy-efficient digital signal processing architectures for Massive MIMO systems, highlighting system-algorithm-hardware co-design, prototype implementations, and future research directions.

Contribution

It provides a comprehensive overview of state-of-the-art techniques and prototypes for low-power Massive MIMO digital processing, emphasizing co-design and hardware innovations.

Findings

Prototype ASIC implementations demonstrate real-time zero-forcing precoding at 55 mW.

Digital processing in antenna paths can be coarse or error-prone, reducing power consumption by 2 to 5 times.

Deeply-scaled silicon technologies enable energy-efficient Massive MIMO processing.

Abstract

Massive MIMO is a compelling wireless access concept that relies on the use of an excess number of base-station antennas, relative to the number of active terminals. This technology is a main component of 5G New Radio (NR) and addresses all important requirements of future wireless standards: a great capacity increase, the support of many simultaneous users, and improvement in energy efficiency. Massive MIMO requires the simultaneous processing of signals from many antenna chains, and computational operations on large matrices. The complexity of the digital processing has been viewed as a fundamental obstacle to the feasibility of Massive MIMO in the past. Recent advances on system-algorithm-hardware co-design have led to extremely energy-efficient implementations. These exploit opportunities in deeply-scaled silicon technologies and perform partly distributed processing to cope with the bottlenecks encountered in the interconnection of many signals. For example, prototype ASIC implementations have demonstrated zero-forcing precoding in real time at a 55 mW power consumption (20 MHz bandwidth, 128 antennas, multiplexing of 8 terminals). Coarse and even error-prone digital processing in the antenna paths permits a reduction of consumption with a factor of 2 to 5. This article summarizes the fundamental technical contributions to efficient digital signal processing for Massive MIMO. The opportunities and constraints on operating on low-complexity RF and analog hardware chains are clarified. It illustrates how terminals can benefit from improved energy efficiency. The status of technology and real-life prototypes discussed. Open challenges and directions for future research are suggested.