A neuromorphic systems approach to in-memory computing with non-ideal memristive devices: From mitigation to exploitation

TL;DR

This paper presents a neuromorphic in-memory computing architecture using memristive devices, addressing device variability through novel circuits and exploiting stochastic switching for improved neural network performance on digit classification tasks.

Contribution

It introduces a mixed-signal interface and a stochastic learning scheme that leverage memristive device variability for neuromorphic computing.

Findings

Variability mitigation via complementary memristive device pairs

Enhanced classification performance with increased memristive devices per synapse

Effective stochastic learning using device intrinsic randomness

Abstract

Memristive devices represent a promising technology for building neuromorphic electronic systems. In addition to their compactness and non-volatility features, they are characterized by computationally relevant physical properties, such as state-dependence, non-linear conductance changes, and intrinsic variability in both their switching threshold and conductance values, that make them ideal devices for emulating the bio-physics of real synapses. In this paper we present a spiking neural network architecture that supports the use of memristive devices as synaptic elements, and propose mixed-signal analog-digital interfacing circuits which mitigate the effect of variability in their conductance values and exploit their variability in the switching threshold, for implementing stochastic learning. The effect of device variability is mitigated by using pairs of memristive devices configured in a complementary push-pull mechanism and interfaced to a current-mode normalizer circuit. The stochastic learning mechanism is obtained by mapping the desired change in synaptic weight into a corresponding switching probability that is derived from the intrinsic stochastic behavior of memristive devices. We demonstrate the features of the CMOS circuits and apply the architecture proposed to a standard neural network hand-written digit classification benchmark based on the MNIST data-set. We evaluate the performance of the approach proposed on this benchmark using behavioral-level spiking neural network simulation, showing both the effect of the reduction in conductance variability produced by the current-mode normalizer circuit, and the increase in performance as a function of the number of memristive devices used in each synapse.