Medusa: A Scalable Interconnect for Many-Port DNN Accelerators and Wide DRAM Controller Interfaces

TL;DR

Medusa is a scalable FPGA interconnect design that efficiently bridges many-port DNN accelerators with wide DRAM controller interfaces, significantly reducing resource usage and increasing frequency.

Contribution

We introduce Medusa, a novel FPGA interconnect that transposes data to match DNN accelerator interfaces, reducing resource consumption and improving performance.

Findings

Reduces LUT and FF usage by 4.7x and 6.0x

Increases interconnect frequency by 1.8x

Addresses the mismatch between DNN and FPGA interfaces

Abstract

To cope with the increasing demand and computational intensity of deep neural networks (DNNs), industry and academia have turned to accelerator technologies. In particular, FPGAs have been shown to provide a good balance between performance and energy efficiency for accelerating DNNs. While significant research has focused on how to build efficient layer processors, the computational building blocks of DNN accelerators, relatively little attention has been paid to the on-chip interconnects that sit between the layer processors and the FPGA's DRAM controller. We observe a disparity between DNN accelerator interfaces, which tend to comprise many narrow ports, and FPGA DRAM controller interfaces, which tend to be wide buses. This mismatch causes traditional interconnects to consume significant FPGA resources. To address this problem, we designed Medusa: an optimized FPGA memory interconnect which transposes data in the interconnect fabric, tailoring the interconnect to the needs of DNN layer processors. Compared to a traditional FPGA interconnect, our design can reduce LUT and FF use by 4.7x and 6.0x, and improves frequency by 1.8x.