Theoretical Model of Computation and Algorithms for FPGA-based Hardware Accelerators

TL;DR

This paper introduces a theoretical model for FPGA-based accelerators, demonstrating algorithms that outperform traditional models and establishing lower bounds for problem-solving times.

Contribution

It presents the first theoretical computation model for FPGA accelerators and develops faster algorithms within this framework.

Findings

Algorithms faster than word-RAM counterparts

Lower bounds on problem-solving times

New techniques for recursive and dynamic algorithms

Abstract

While FPGAs have been used extensively as hardware accelerators in industrial computation, no theoretical model of computation has been devised for the study of FPGA-based accelerators. In this paper, we present a theoretical model of computation on a system with conventional CPU and an FPGA, based on word-RAM. We show several algorithms in this model which are asymptotically faster than their word-RAM counterparts. Specifically, we show an algorithm for sorting, evaluation of associative operation and general techniques for speeding up some recursive algorithms and some dynamic programs. We also derive lower bounds on the running times needed to solve some problems.