A New Paradigm for Fault-Tolerant Computing with Interconnect Crosstalks

TL;DR

This paper introduces a novel crosstalk logic-based polymorphic circuit approach that enhances fault tolerance in integrated circuits by enabling multiple functionalities with reduced hardware overhead, outperforming traditional methods.

Contribution

The paper presents a new polymorphic circuit design using crosstalk logic, achieving compact, efficient fault resilience with significant reductions in transistor count compared to existing techniques.

Findings

Achieved 28% reduction in transistor count over existing polymorphic techniques.

Demonstrated a functional unit capable of multiple operations depending on control inputs.

Showed potential for fault-tolerant ALUs with minimal overhead.

Abstract

The CMOS integrated chips at advanced technology nodes are becoming more vulnerable to various sources of faults like manufacturing imprecisions, variations, aging, etc. Additionally, the intentional fault attacks (e.g., high power microwave, cybersecurity threats, etc.) and environmental effects (i.e., radiation) also pose reliability threats to integrated circuits. Though the traditional hardware redundancy-based techniques like Triple Modular Redundancy (TMR), Quadded (QL) Logic etc. mitigate the risk to some extent, they add huge hardware overhead and are not very effective. Truly polymorphic circuits that are inherently capable of achieving multiple functionalities in a limited footprint could enhance the faultresilience/recovery of the circuits with limited overhead. We demonstrate a novel crosstalk logic based polymorphic circuit approach to achieve compact and efficient fault resilient circuits. We show a range of polymorphic primitive gates and their usage in a functional unit. The functional unit is a single arithmetic circuit that is capable of delivering Multiplication/Sorting/Addition output depending on the control inputs. Using such polymorphic computing units in an ALU would imply that a correct path for functional output is possible even when 2/3rd of the ALU is damaged. Our comparison results with respect to existing polymorphic techniques and CMOS reveal 28% and 62% reduction in transistor count respectively for the same functionalities. In conjunction with fault detection algorithms, the proposed polymorphic circuit concept can be transformative for fault tolerant circuit design directions with minimum overhead.