Crosstalk based Fine-Grained Reconfiguration Techniques for Polymorphic Circuits

TL;DR

This paper introduces a novel crosstalk-based polymorphic circuit design that leverages nano-metal line interference for logic and configuration, significantly reducing transistor count compared to existing approaches.

Contribution

It presents a new deterministic interference-based method for designing polymorphic circuits using nano-metal lines and a control metal line, achieving lower transistor counts.

Findings

Significant transistor count reduction (25%-83%) compared to existing approaches.

Demonstrated a wide range of crosstalk polymorphic logic gates.

Showcased a large circuit performing multiple functions based on configuration.

Abstract

Truly polymorphic circuits, whose functionality/circuit behavior can be altered using a control variable, can provide tremendous benefits in multi-functional system design and resource sharing. For secure and fault tolerant hardware designs these can be crucial as well. Polymorphic circuits work in literature so far either rely on environmental parameters such as temperature, variation etc. or on special devices such as ambipolar FET, configurable magnetic devices, etc., that often result in inefficiencies in performance and/or realization. In this paper, we introduce a novel polymorphic circuit design approach where deterministic interference between nano-metal lines is leveraged for logic computing and configuration. For computing, the proposed approach relies on nano-metal lines, their interference and commonly used FETs, and for polymorphism, it requires only an extra metal line that carries the control signal. In this paper, we show a wide range of crosstalk polymorphic (CT-P) logic gates and their evaluation results. We also show an example of a large circuit that performs both the functionalities of multiplier and sorter depending on the configuration signal. Our benchmarking results are presented in this paper. For CT-P, the transistor count was found to be significantly less compared to other existing approaches, ranging from 25% to 83%. For example, CT-P AOI21-OA21 cell show 83%, 85% and 50% transistor count reduction, and MultiplierSorter circuit show 40%, 36% and 28% transistor count reduction with respect to CMOS, genetically evolved, and ambipolar transistor based polymorphic circuits respectively.